TSM
- guest (Chris Auth, Intel process development) 15:04Intel's process lead says backside power lets 14A use High-NA EUV in a single pass, while TSMC without backside power would still need double-patterned EUV.
- guest (Intel CTO Pushkar Ranade) 56:08Intel's CTO says Intel is already within a few percent of TSMC on performance, power or density and that the remaining gap is wafer scale.
- host 2:22TSMC's CEO said on its earnings call that TSMC is looking at Texas and talking to Terafab about using some of its spare capacity.
- host 11:25TSMC said on its earnings call that it sends its own employees to data centers to check how far along they are.TSM novelty 2/3 · verifiable 3/3